Testing a logic circuit is often performed by loading test data into the logic circuit and, in a controlled manner, advancing the logic circuit from state to state. Various test data is output from the logic circuit and examined to determine whether the logic circuit is functioning as expected. Special scan test input/output pins are often provided for the input and output of the test data. Both parallel and serial designs exist for scanning-in and scanning-out test data via the scan test input/output pins. Parallel designs decrease the time required to load test data and read test results at the expense of increased pin resources. Serial designs conserve pin resources, but require additional time to load test data and read test results as compared to parallel designs.
Increasing levels of circuit integration create at least two problems for scan testing logic circuits. First, as the number of functional blocks of logic circuits on a chip increases, the length of scan paths and the quantity of test data increase. Increased scan paths create layout complexity and increase costs, and more test data typically leads to increased test complexity. A second problem is that a greater number of functional blocks of logic circuits on a chip creates increased demand for input/output pins for circuit access during normal operation, thereby competing with input/output pins used exclusively for scan testing.
Cost-effective and efficient solutions for scan testing are highly desirable for the aforementioned reasons. However, present designs often trade pin resources against test time in implementing a desired level of cost-effectiveness and efficiency.